1. Field of the Invention
In general, the present invention relates to a pixel selection control method, driving circuit, display apparatus and electronic instrument. More particularly, the present invention relates to a flat-panel display apparatus employing pixels which each include an electro-optical device and are laid out 2-dimensionally to form a matrix, relates to a method for driving the display apparatus and relates to electronic apparatus each having the display apparatus.
2. Description of the Related Art
The existing display apparatus employs pixels which each include an electro-optical device and are laid out 2-dimensionally to form a pixel matrix. The display apparatus has a row scan section for selecting pixels laid out along a pixel row of the pixel matrix by activating a scan line connected to the pixels laid out along the pixel row. That is to say, the row scan section selects pixels in row units. Typically, the row scan section employs a shift register or a decoder and a level conversion circuit which is also referred to as a level shift circuit. The level shift circuit is a circuit for changing the amplitude of a scan signal output by the shift register or the decoder to an amplitude which is required for driving the electro-optical devices. The level shift circuit is provided for every pixel row of the matrix or every scan line.
With a level shift circuit provided for every scan line as described above, however, the timing of a scan signal generated by a level shift circuit is different from the timing of a scan signal generated by another level shift circuit. This difference in timing between scan signals generated by different level shift circuits is caused by variations of characteristics of the same circuit devices employed in the different level shift circuits. This difference in timing between scan signals generated by different level shift circuits has a variety of bad effects on the image displayed by the display apparatus.
In order to solve the problem raised by the existing display apparatus as described above, the scan signals are provided with a common enable signal for prescribing rising and falling timings of every scan signal. In such a configuration, the enable signal and the scan signals are subjected to logic processing in order to eliminate variations of timing between the scan signals which are generated by different level shift circuits. For details, the reader is suggested to refer to documents such as Japanese Patent Laid-open No. 2008-286963.
FIG. 30 is a block diagram showing a typical configuration of a row scan section 300 employed in the existing display apparatus. As shown in FIG. 30, the row scan section 300 employed in the existing display apparatus has level shift circuits 301, 302 and 303, a shift register section 304, a first logic circuit section 305, a level shift circuit section 306, a second logic circuit section 307 and a buffer section 308. In order to make FIG. 30 simple, the typical configuration of the row scan section 300 is shown to include sections provided for four pixel rows which start with the first pixel row.
In the typical configuration shown in FIG. 30, shift signals are output sequentially from unit circuits of the shift register section 304. In the following description, each of the shift signals is also referred to as a reference signal. Each of the unit circuits is also referred to as an S/R (shift register) or a transfer register. The shift register section 304 supplies the shift signals to the second logic circuit section 307 by way of the first logic circuit section 305 and the level shift circuit section 306. The level shift circuit section 306 changes the amplitude of each of the shift signals to an amplitude which is required for driving electro-optical devices not shown in FIG. 30. The level shift circuit section 306 supplies every signal having the amplitude required for driving electro-optical devices to a specific input node of each of AND gates 307-1 to 307-4 which are employed in the second logic circuit section 307.
The other input node of each of the AND gates 307-1 to 307-4 is connected to a common transmission line SL which is provided to serve as a line common to all pixel rows. The common transmission line SL is used for supplying a vertical enable signal VEN, the level of which has been changed by the level shift circuit 303. Each of the AND gates 307-1 to 307-4 generates a scan signal which represents the logical product of the shift signal and the vertical enable signal VEN. That is to say, the second logic circuit section 307 sequentially generates scan signals with rising and falling timings which are determined by the vertical enable signal VEN. The second logic circuit section 307 supplies the scan signals to their respective row scan lines for their respective pixel rows by way of the buffer section 308. It is to be noted that the row scan lines are not shown in FIG. 30.